Precision Timing ASIC: a recent example from CMS MTD Endcap Timing Layer (ETL) upgrade

The precision position detectors (such as silicon strip and pixel detectors) have been very successful over the past few decades for hadron collider experiments, from the top quark discovery at Fermilab in the 1990s to the Higgs discovery at CERN. As luminosity increases, the pileup increases so much and just using precision position information is not enough to separate the pileup events, and precision timing information will be needed. This is the reason that the first generation of LGAD (Low-Gain Avalanche Detector) based precision timing detectors has been added to the HL-LHC upgrade for both CMS and ATLAS. In this talk, the development of the precision timing ASIC for CMS ETL will be presented, the so called ETROC (Endcap Timing ReadOut Chip). The ETROC is designed to process LGAD signals with time resolution down to ~ 40-50ps per hit to achieve ~30-35ps per track with two-layer detectors, and its dimensions are 21mm x 23mm making it one of the largest chips in HEP. The talk will discuss the early design choices with a top-down and bottom-up approach based on the physics goals and detector constrains for ETROC specification studies, the chip development experiences and the extensive testing of bump bonded ETROC/LGAD with lessons learned along the way.  Additional ETROC capabilities, such as precision on-chip clock distribution network, in-pixel automatic calibration, waveform sampling for monitoring purpose, as well as time-walk correction uniformity, and selftriggering capability for long-lived particle searches will be presented. Towards the end, I will also comment on the future prospect of precision timing and position detector design issues and the challenges ahead when we try to scale the pixel size down, based on what we have learned from the ETROC design experience as well as on going R&D work.