Future Colliders

Abstract:

The “APC3” is a charge sampling and storage chip designed for high speed readout of silicon detectors. It has 32 channels, each with preamplifier, integrator and storage capacitors. Current from a silicon detector connected to the input is integrated as a charge and stored on a capacitor. There are 128 capacitors per channel which are used sequentially to store the charge. The charge is held on the storage capacitor until it is either read out or discarded. Logic on the chip manages the storage and retrieval of samples. This logic uses a novel architecture based on a system of pointers and read out addresses. This paper describes the operation of the chip and measurements of its performance. © 1994 IEEE

Abstract:

The Central Tracking Detector (CTD) of the ZEUS experiment uses a Flash Analogue to Digital Converter (FADC) readout system to measure the arrival time of ionisation at sense wires as well as the charge deposited. A digitisation frequency of 104 MHz is used and the data is written to pipelined data stores. A Digital Signal Processor (DSP) is used to control the main functions on the card as well as perform data parameterisation and compression. Test and operational performance results from the first electron-proton interactions are presented. © 1994 IEEE

Abstract:

The Tracking Detector time resolution of 2ns and the 96ns periodic interaction of protons and electrons of the HERA collider require real time data acquisition at 104MHz controlled reliably to tight tolerances. Maximum event readout efficiency, fast monitoring of run time errors and testability of front end electronics require pipelining, speed and flexibility. Such an electronic Timing and control system (TCS) is operational within three main inner detectors of the ZEUS detector and is presented in this paper.