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Largest layer of SCT barrel detector

The largest radius layer of the SCT barrel detector after all SCT modules had been mounted in a clean room in the physics department.

Professor Tony Weidberg

Senior Researcher

Research theme

  • Fundamental particles and interactions

Sub department

  • Particle Physics

Research groups

  • ATLAS
Tony.Weidberg@physics.ox.ac.uk
Telephone: 01865 (2)73370
Denys Wilkinson Building, room 629
  • About
  • Publications

Frequency scanned interferometry (FSI): The basis of a survey system for ATLAS using fast automated remote interferometry

NUCL INSTRUM METH A 383:1 (1996) 229-237

Authors:

AF FoxMurphy, DF Howell, RB Nickerson, AR Weidberg

Abstract:

A novel optical survey system for continuous alignment of HEP experiments is described. The complete survey system is outlined and the underlying measurement technique, FSI, is described in detail. Preliminary findings made with a laboratory demonstration system for FSI are presented.
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A life time test of neutron irradiated light emitting diodes

Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 373:3 (1996) 320-324

Authors:

J Beringer, K Borer, CB Brooks, A Fox-Murphy, RB Nickerson, AR Weidberg

Abstract:

The results of an accelerated life time test of neutron irradiated ABB Hafo radiation hard LEDs are presented. After a 1 MeV neutron irradiation with up to 1.4 × 1014 n/cm2 at the Rutherford Appleton Lab (RAL) ISIS facility, the LEDs have been operated without seeing any degradation due to ageing for a time which is estimated to correspond to about 57 years of operation in the ATLAS Semiconductor Tracker (SCT) at the Large Hadron Collider (LHC). The irradiation decreased the light output of the LEDs substantially, but during the operation of the LEDs a fast annealing of most of the irradiation damage was observed.
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Characteristics of a 'HARP' signal processor with analog memory operated with segmented silicon detectors

IEEE Transactions on Nuclear Science Institute of Electrical and Electronics Engineers (IEEE) 41:4 (1994) 1130-1134

Authors:

F Anghinolfi, P Aspell, R Bonino, K Borer, D Campbell, M Campbell, AG Clark, C Gossling, P Jarron, EHM Heijne, H Kambara, B Lisowski, GF Moorhead, P Murray, JC Santiard, GN Taylor, J Teiger, H Verweij, A Weidberg, X Wu
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Electronics and readout of a large area silicon detector for LHC

Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment Elsevier 344:1 (1994) 185-193

Authors:

K Borer, DJ Munday, MA Parker, F Anghinolfi, P Aspell, M Campbell, A Chilingarov, P Jarron, EHM Heijne, JC Santiard, P Scampoli, H Verweij, C Gössling, B Lisowski, A Reichold, R Spiwoks, E Tsesmelis, K Benslama, R Bonino, AG Clark, C Couyoumtzelis, H Kambara, X Wu, E Fretwurst, G Lindstroem, T Schultz, RA Bardos, GW Gorfine, GF Moorhead, GN Taylor, SN Tovey, JH Bibby, RJ Hawkings, N Kundu, A Weidberg, D Campbell, P Murray, P Seller, J Teiger
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APC3-A Charge Sampling, Storage & Readout Chip for Silicon Detector Readout RD2 Collaboration

IEEE Transactions on Nuclear Science 41:4 (1994) 1091-1094

Authors:

K Borer, DJ Munday, MA Parker, F Anghinolfi, P Aspell, M Campbell, P Jarron, EHM Heijne, JC Santiard, H Verweij, C Gößling, A Reichold, R Bonino, AG Clark, H Kambara, DL Marra, A Leger, JP Richeaux, X Wu, F Fares, J Bibby, A Weidberg, D Campbell, P Murray, P Seller, M Rouget, J Teiger

Abstract:

The “APC3” is a charge sampling and storage chip designed for high speed readout of silicon detectors. It has 32 channels, each with preamplifier, integrator and storage capacitors. Current from a silicon detector connected to the input is integrated as a charge and stored on a capacitor. There are 128 capacitors per channel which are used sequentially to store the charge. The charge is held on the storage capacitor until it is either read out or discarded. Logic on the chip manages the storage and retrieval of samples. This logic uses a novel architecture based on a system of pointers and read out addresses. This paper describes the operation of the chip and measurements of its performance. © 1994 IEEE
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