Abstract:

The performance of a prototype Ring Imaging Cherenkov Detector is studied using a charged particle beam. The detector performance, using CF4 and air as radiators, is described. Cherenkov angle precision and photoelectron yield using hybrid photo-diodes and multi-anode PMTs agree with simulations and are assessed in terms of the requirements of the LHCb experiment.

Abstract:

The development of a front-end readout system for the LHCb Ring Imaging Cherenkov (RICH) detectors is in progress. The baseline choice for the RICH photon detector front-end electronics is a binary readout ASIC for an encapsulated silicon pixel detector. This paper describes a system to transmit the binary data with address ID and error codes, from a radiation harsh environment while keeping synchronisation. The total data read out for the fixed Level-0 readout period of 900ns is 32x36x440 non-zero-suppressed bits per Level-0 trigger, with a sustained Level-0 trigger rate of 1MHz. Multimode fibres driven by VCSEL devices are used to transmit data to the off-detector Level-1 electronics located in a non-radiation environment. The data are stored in 512Kbit deep QDR buffers.

Abstract:

This paper summarizes the recent progress in the development of the 128 channel pipelined readout chip Beetle, which is intended for the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detectors(1) of LHCb.Deficiencies found in the front end of the Beetle Version 1.0 and 1.1 chips resulted in the submissions of BeetleFE 1.1 and BeetleFE 1.2, while BeetleSR 1.0 implements test circuits to provide future Beetle chips with logic circuits hardened against single event upset (SEU).Section I. motivates the development of new front ends for the Beetle chip, and section II. summarizes their concepts and construction. Section III. reports preliminary results from the BeetleFE 1.1 and BeetleFE 1.2 chips, while section IV. describes the BeetleSR 1.0 chip. An outlook on future test and development of the Beetle chip is given in section V.

Abstract:

This paper details the development steps of the 128 channel pipelined readout chip Beetle, which is being designed for the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detectors(1) of LHCb. Section II. summarizes the Beetle chip architecture.Section III. shows the key measurements on the first chip version (Beetle 1.0) which drove the design changes for the Beetle 1.1. First performance data of the new chip is presented in section IV., while an outlook on the future test and development of the chip are given in section V.