Rui Gao

Abstract:

We have tested the first 4T Monolithic Active Pixel Sensor (MAPS) for particle physics, FORTIS in a beam test. We have measured a signal-to-noise ratio of more than 100 for MIPs due to the excellent noise performance of the 4T architecture. Two versions of the sensor were tested; with and without deep P-well areas in-pixel. The deep P-well areas allow the incorporation of PMOS transistors inside the pixels without signal charge loss. The measured position resolutions were around 2 μm. © 2011 IOP Publishing Ltd and SISSA.

Abstract:

The vertex detectors at the International Linear Collider (ILC) (there will be two of them, one for each of two general purpose detectors) will certainly be built with silicon pixel detectors, either monolithic or perhaps vertically integrated. However, beyond this general statement, there is a wide range of options supported by active R&D programmes all over the world. Pixel-based vertex detectors build on the experience at the SLAC large detector (SLD) operating at the SLAC linear collider (SLC), where a 307 Mpixel detector permitted the highest physics performance at LEP or SLC. For ILC, machine conditions demand much faster readout than at SLC, something like 20 time slices during the 1 ms bunch train. The approach of the image sensor with in-situ storage (ISIS) is unique in offering this capability while avoiding the undesirable requirement of 'pulsed power'. First results from a prototype device that approaches the pixel size of 20 μm square, needed for physics, are reported. The dimensional challenge is met by using a 0.18 μm imaging CMOS process, instead of a conventional CCD process. © 2010 Elsevier B.V. All rights reserved.

Abstract:

ISIS (In-situ Storage Imaging Sensor) is a novel CMOS sensor with multiple charge storage capability developed for the ILC vertex detector by the Linear Collider Flavour Identification (LCFI) collaboration. This paper reports test results for ISIS2, the second generation of ISIS sensors implemented in a 0.18 micron CMOS process. The local charge storage and charge transfer were unambiguously demonstrated.

Abstract:

The Linear Collider Flavour Identification (LCFI) Collaboration is developing the sensors, readout electronics and mechanical support structures for the vertex detector of the International Linear Collider (ILC). High speed readout is needed to ensure that the occupancy due to the pair production background at the ILC is kept below the 1% level. In order to satisfy this requirement, Column Parallel CCDs (CPCCDs), Column Parallel Readout chips (CPRs) and Column Parallel Driver chips (CPDs) have been developed. The CPCCD has to operate at a clock frequency of 50 MHz, which represents a difficult technical challenge due to the large sensor capacitance. The design and performance of the second generation CPCCD sensors, CPC2, and the new driver chip, CPD1, which meet these challenging requirements, are described. © 2010 Elsevier B.V. All rights reserved.