Rui Gao

Abstract:

The LCFI Collaboration is developing the sensors, readout electronics and mechanical support structures for the Vertex Detector (VXD) of the International Linear Collider (ILC). High-speed readout is needed to ensure that the occupancy due to the pair production background at the ILC is kept below 1% level. In order to satisfy this requirement, Column Parallel CCDs (CPCCDs) and Column Parallel Readout chips (CPRs) have been developed. The CPCCD has to operate at a clock frequency of 50 MHz, which represents a difficult technical challenge due to the relatively large sensor capacitance. The design and performance of planar transformers, which can be used to provide the required 20 A clock current, are described. © 2009 Elsevier B.V. All rights reserved.

Abstract:

The Linear Collider Flavour Identification (LCFI) collaboration has successfully developed the first prototype of a novel particle detector, the In-situ Storage Image Sensor (ISIS). This device ideally suits the challenging requirements for the vertex detector at the future International Linear Collider (ILC), combining the charge storing capabilities of the Charge-Coupled Devices (CCD) with readout commonly used in CMOS imagers. The ISIS avoids the need for high-speed readout and offers low power operation combined with low noise, high immunity to electromagnetic interference and increased radiation hardness compared to typical CCDs. The ISIS is one of the most promising detector technologies for vertexing at the ILC. In this paper we describe the measurements on the charge-shielding properties of the p-well, which is used to protect the storage register from parasitic charge collection and is at the core of device's operation. We show that the p-well can suppress the parasitic charge collection by almost two orders of magnitude, satisfying the requirements for the application. Crown Copyright © 2009.

Abstract:

In the past year, the Linear Collider Flavour Identification (LCFI) Collaboration has taken significant steps towards having a sensor suitable for use in the silicon vertex detector of the International Linear Collider (ILC). The goal of the collaboration is to develop the sensors, electronic systems and mechanical support structures necessary for the construction of a high performance vertex detector and to investigate the contribution such a vertex detector can make to the physics accessible at the ILC. Particular highlights include the delivery and testing of both a second-generation column parallel CCD (CP-CCD), design of the next-generation readout ASIC (CPR2a) and a dedicated ASIC for driving the CP-CCD. This paper briefly describes these and other highlights. (c) 2007 Elsevier B.V. All rights reserved.

Abstract:

As programmable hardware technology gathers momentum, the partitioning of applications into hardware and software will prove to be an increasingly important research area,. Co-design technologies that achieve this partitioning typically adopt a strategy in which a high level specification is used to synthesise both hardware and software. This paper proposes an alternative approach by which equivalencies between hardware and software components are defined, thereby providing a, common interface between them. This allows logic to be moved between hardware and software while retaining the functional properties of the application. An investigation is carried out to derive equivalencies between software elements of the Java, language and hardware components by appropriate wrapping of the latter. By developing a framework that captures these equivalencies, this paper shows how hardware/software partitioning of a system can be relegated to a, late stage of system development and include both application and virtual machine logic. Copyright 2006 ACM.

Abstract:

Networks for real-time embedded systems are a key emerging technology for current and future systems. Such networks need to enable reliable communication without requiring significant resources, and provide an easy programming interface. This paper considers a file-system interface across all resources in a networked embedded system, ie. an application can access local, remote and mobile resources using a file interface. The approach is based on Styx [1,2], part of the network protocol of the Inferno/Plan 9 OS [1]. The Styx protocol provides file system level abstractions for ease of developing and management at an application layer. To this, we have added limited fault-tolerance and potential mobility for resources. To ensure applicability in a low-resource context, we have defined and implemented a (hardware) Styx IP-core Module ¹, removing the need for a CPU and software overhead. © 2006 IEEE.