Rui Gao

Abstract:

Application level interoperability between ubiquitous networked communication devices (e.g. Mobile phones, PDA, CCD camera, etc.) poses many problems. In this paper we consider the issue of efficient application level access to resources on remote devices whilst achieving both network and distribution transparency. Provision of such transparency is difficult as low-resource devices are usually limited to one or two standard communication mediums (e.g. WiFi, Bluetooth, ZigBee). Thus, it is unlikely that an application node can communicate directly with all other nodes, with the requirement for some to act as intermediaries. Also, direct control of remote devices (potentially via some intermediary) in the same manner as local devices is not usually provided by conventional OSs. In this paper we consider the Styx protocol (from the Inferno OS) as a solution to these problems. Styx is defined to provide a file based interface to devices, within a namespace that provides distribution transparency (coping with intermediary devices). However, Styx currently is only available as software, requiring a OS (and CPU). We define and implement a (hardware) Styx IP-core Moduleι to provide both network and distribution transparency for applications that control physically remote devices. For lowresource devices, such an approach removes the need for a CPU (to execute a software OS and Styx implementation). The implementation of the hardware Styx IP-core (and subsequent demonstration) presented within the paper show the efficacy of this hardware Styx approach.

Abstract:

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.